The present invention relates to an optical time domain reflectometer (hereinafter referred to as an OTDR) and, in particular, to an OTDR for inputting a light pulse into an optical fiber line path and finding an intensity variation of returned light from the optical fiber line path with respect to a time in which the OTDR adopts a technique for achieving an enhanced distance accuracy.
In the case where the test of a communication system using an optical fiber line path is carried out, use is made of an OTDR 10 having a structure as shown in FIG. 7.
That is, this OTDR 10 is so configured as to input a light pulse from a light pulse generation section 12 through a directional couper 11 to an optical fiber line path 1 as a to-be-tested object connected to a connection terminal 10a, receive the light which is returned back from the optical fiber line path 1 at a light receiving unit 13 via-the directional coupler 11, and, while sampling the receiving signal by an analog/digital (A/D) converter 14 with a predetermined frequency, convert it to a digital value.
And this OTDR 10 finds a digital value which is outputted from the A/D converter 14 until a predetermined time elapses from the inputting of the light pulse, as data representing the transmission characteristic of the optical fiber line path 1.
It is to be noted that, in FIG. 7, a measurement control circuit 15 outputs a drive pulse Pd to the light pulse generation section 12 to allow a light pulse to exit in synchronism with the drive pulse Pd while, on the other hand, the control circuit 15 outputs a sampling pulse PS of a predetermined period to the A/D converter 14 a predetermined number of times to allow the sampling of a receiving signal.
In the OTDR 10 thus configured, a resolution as to the time determines a resolution as to the distance of the characteristic of the optical fiber line path 1.
In order to make measurement with a high distance resolution it is necessary to make the period of the sampling pulse Ps of the A/D converter 14 smaller.
However, there is a limitation to the sampling speed of the A/D converter 14 and, in order to maintain the accuracy of the data higher, a problem arises from the fact that it is not preferable to increase the sampling speed up to its limit.
In order to solve this problem, the conventional OTDR 10 does the following.
First, in order to find the characteristic of one optical fiber line path 1 a drive pulse Pd of a predetermined width is outputted an M number of times (it is assumed that M=5) as shown in FIG. 8A.
And, as shown in FIGS. 8B-F, respective N numbers of sampling pulses Ps (1), Ps (2), . . . , Ps (5) are outputted to the A/D converter 14 while delaying their output start timing by a predetermined time xcex94T (1/M of a period T of the sampling pulse Ps) with respect to the output timing of the drive pulse Pd at each number of times.
The system of obtaining a series of data by shifting the sampling start timing by xe2x80x9c1/an integral numberxe2x80x9d of the period of the sampling pulse with respect to the analog signal repeatedly inputted with the same waveform is generally called as an interleave sampling.
By performing such sampling based on this interleave sampling it is possible to obtain data equivalent to the case when a signal received from the incidence of the light pulse into the optical fiber line path 1 until the passage of an Nxc2x7Txe2x88x92xcex94T time is Mxc2x7N times continuously sampled with a period xcex94T shorter than a period T of the sampling pulse PS, as shown in FIG. 8G.
That is, the sampling speed of the A/D converter 14 can be made equivalent to that multiplied M times.
In order to relatively delay the output start timing of the sampling pulse Ps by a predetermined time xcex94T in this way, the conventional OTDR 10 includes the measurement control circuit 15 configured as shown in FIGS. 9 and 10.
In the structure as shown in FIG. 9, a clock signal generation circuit 16 generates a clock signal CKr of a predetermined period T as a reference.
This clock signal CKr is input to a drive pulse generation circuit 17 and to a plurality of delay elements 18 (1), 18 (2), . . . , 18 (M).
The drive pulse generation circuit 17 is so configured that, upon receipt of a start signal for designating a measurement start, it outputs a drive pulse Pd of a predetermined time width, an M number of times, in synchronization with the clock signal CKr with a period longer than N times the period T of the clock signal CKr.
The delay elements 18 (1), 18 (2), . . . , 18 (M) output the inputted clock signals CKr to the select circuit 19 while being delayed by 0, xcex94T, 2xcex94T/, . . . , (Mxe2x88x921) xcex94T.
The select circuit 19 selectively provides, as a sampling pulse Ps, an output out of these outputs of the delay elements 18 (1), 18 (2), . . . , 18 (M) which is designated from a switching circuit 20.
The switching circuit 20 sets the select circuit 19 in a non-select state until receiving a start signal and, upon receipt of the start signal, causes the select circuit 19 to select an output of the delay circuit 18 (1).
When, by doing so, an N number of sampling pulses Ps are outputted from the select circuit 19, the switching circuit 20 again sets the select circuit 19 in a non-select state.
And the switching circuit 20 causes the output of the delay element 18 (2) to be selected by the select circuit 19 upon receipt of the next drive pulse as an output pulse.
By doing so, when a predetermined N number of sampling pulses Ps are outputted from the select circuit 19, the switching circuit 20 again sets the select circuit 19 in a non-select state.
In the same way as set out above, the switching circuit 20 causes the select circuit 19 to select the outputs of the delay elements 18 (3), . . . , 18 (M).
When the output of the last delay element 18(M) is selected by the select circuit 19 and the predetermined number N of sampling pulses Ps are outputted, then the switching circuit 20 causes the select circuit 19 to be set to the non-select state, thus waiting for the inputting of the next start signal.
By the select operation by the switching circuit 20 of the delay elements 18 (1), 18 (2), . . . , 18 (M) it is possible to provide respective N numbers of sampling pulses Ps (1), Ps (2), . . . , Ps (M), as shown in FIGS. 8A to G, to the A/D converter 14 while delaying the output start timing by a predetermined time xcex94T with respect to the output timing of the drive pulse Pd at each number of times.
In an arrangement shown in FIG. 10, a clock signal CKr outputted from a clock signal generation circuit 16 is divided by a frequency divider 21 into, for example, four frequency division parts which are inputted as a frequency divided signal CKd to an integrating circuit 22.
The integrating circuit 22 integrates the frequency divided signal CKd and outputs a ramp function signal V (=xcex1t) for example, with a voltage V increasing from 0 volt in proportion (proportional constant xcex1) to a time t with its high level time point as a reference.
The ramp function signal V, together with a reference voltage Vr from a reference voltage generator 23, is inputted to a comparator 24 where comparison is made between the ramp function signal V and the reference voltage Vr.
At a timing that the ramp function signal V coincides with the reference voltage Vr and the output of the comparator 24 is inverted, a drive pulse generation circuit 17 outputs a drive pulse Pd of a predetermined width while, on the other hand, a sampling pulse generation circuit 25 starts to output an N number of sampling pulses Ps in synchronization with the clock signal CKr.
Until receiving a start signal, the switching circuit 26 sets the reference voltage Vr which is outputted from the reference voltage generator 23 to a voltage higher than a maximal value of the ramp function signal V outputted from the integrating circuit 22 to prevent the output of the comparator 24 from being set in a non-inverting state.
Upon receipt of the start signal, the switching circuit 26 sets the reference voltage Vr to, for example, xcex1xc2x72T during the low level period of the frequency divided signal CKd and, when a 2T time is passed after the frequency divided signal CKd rises to a high level, the output of the comparator 24 is inverted to allow a drive pulse Pd to be outputted and an N number of sampling pulses Ps (1) to start being outputted with its initial pulse put in synchronization with the drive pulse Pd.
It is to be noted that, when the frequency divided signal CKd becomes a low level while the N number of sampling pulses Ps are outputted, the switching circuit 26 sets the reference voltage Vr to a voltage higher than a maximal value of the ramp function signal V and, by doing so, prevents the output of the comparator 24 from being set to a non-inverted state.
During the low level period of the frequency divided signal CKd following the outputting of this first N number of sampling pulses Ps, the switching circuit 26 sets the reference voltage Vr to xcex1 (2Txe2x88x92xcex94T) and, upon the elapsing of a (2Txe2x88x92xcex94T) time after the frequency divided signal CKd rises to a high level, inverts the output of the comparator 24 to allow the drive pulse Pd to be outputted and the outputting of an N number of sampling pulses Ps (2) to be started while being delayed by xcex94T from the output timing of the drive pulse Pd.
In the same way as set out above, the switching circuit 26 switches the reference voltage Vr to xcex1(2Txe2x88x922xcex94T), xcex1 (2Txe2x88x923xcex94T), xcex1 (2Txe2x88x924xcex94T), . . . , xcex1 (T+xcex94T) to allow the outputting of the N number of sampling pulses Ps to be started while being delayed by 2xcex94T, 3xcex94T, 4xcex94T, . . . , (Txe2x88x92xcex94T) from the output timing of the drive pulse Pd and, by doing so, as shown in FIGS. 8A to G, respective N numbers of sampling pulses Ps (1), Ps (2), . . . , Ps (M) are outputted to the A/D converter 14 while delaying their output start timings by xcex94T with respect to the output timing of the drive pulse Pd at each number of times.
However, the time accuracy of such ordinary delay element as used in the arrangement shown in FIG. 9 is very low and it currently has an accuracy limit of several nanoseconds and, in order to obtain more time resolution, it is necessary to use a cable""s delay function.
Incidentally, the delay element using the cable is structurally difficult to manufacture as a smaller unit.
Further, the system using the switching of such delay elements as set out above requires a greater number of elements as the time resolution is enhanced, so that a resultant apparatus becomes bulkier.
In the structure as shown in FIG. 10 in which the clock signal (frequency divided signal) is integrated by the integrating circuit 22 and its output voltage is compared by the comparator 24 with the reference voltage Vr, the accuracy of the delay time is lowered due to the nonlinearity of the integrating circuit 22, thus presenting a problem.
It is accordingly the object of the present invention to solve the above-mentioned problems and to provide an OTDR which can be constructed as a compact unit with high accuracy.
According to one embodiment of the present invention, there is provided an OTDR comprising:
a light pulse generation section (12) for receiving a drive pulse and generating a light pulse in synchronization with the drive pulse;
light branching means (11) for causing the light pulse which exits from the light pulse generation section to be incident into an optical fiber line path (1) as an object of testing, and for taking out returned light from the optical fiber line path;
a light receiving unit (13) for receiving the returned light taken out by the light branching means and converting it to a light receiving signal;
an A/D converter (14) for receiving a sampling pulse of a period T0 and, while subjecting the light receiving signal to equivalent sampling in synchronization with the sampling pulse, converting it to digital data;
a measurement control circuit (31) for generating the drive pulse a plurality of (M) times and outputting it to the light pulse generation section and for generating respective N numbers of sampling pulses relative to an output timing of the drive pulse at each number of times and outputting the sampling pulses to the A/D converter while delaying the respective N generation start timings by xcex94T corresponding to 1/M of the period T0;
clock signal generating means (32) for outputting, to the measurement control circuit, a first clock signal of a period T1 and a second clock signal having a period difference xcex94t equal to a time corresponding to a minimal resolution required of the OTDR relative to the period T1; and
data processing means (48) for obtaining a series of data representing an intensity variation relative to a time elapse of the returned light on the basis of the digital data outputted from the A/D converter, wherein
the measurement control circuit provides a delay of the time xcex94T of the sampling pulse on the basis of a period difference xcex94t of the first clock signal and second clock signal from the clock signal generating means.